//==============================================================================
//
//  File        : mmp_register_usb.h
//  Description : INCLUDE File for the USB register map.
//  Author      : Ben Lu
//  Revision    : 1.0
//
//==============================================================================



#ifndef _MMP_REG_USB_H_
#define _MMP_REG_USB_H_
#if (CHIP == P_V2)||(CHIP == VSN_V2)
#include    "mmp_register.h"
/*
#define     USB_DMA_BASE_ADDR		(0x80001400)  //USB DMA registers base address
#define 	USB_CTL_BASE_ADDR		(0x80001000)  //USB control registers base address
*/
/** @addtogroup MMPH_reg
@{
*/

// *****************************************************************************
//   USB base control register structure (0x8000 6000)
// *****************************************************************************
typedef struct _AITS_USB_DMA {
    AIT_REG_B   USB_CTL_SEL;                                          	// 0x00
   	AIT_REG_B   USB_SIDDQ;                                          	// 0x01
   	AIT_REG_B   USB_LOP_CTL;                                          	// 0x02
   	AIT_REG_B   USB_UTMI_WRA_CTL;                                       // 0x03
   	AIT_REG_B   USB_PLL_CTL;                                          	// 0x04
   	AIT_REG_B   USB_XO_CTL;                                          	// 0x05
   	AIT_REG_B   USB_PHY_PROBE_SEL;                                      // 0x06
   	AIT_REG_B   USB_TRCV_TM_CTL;                                        // 0x07
   	AIT_REG_B   USB_POR_BYPASS;                                 		// 0x08
   	AIT_REG_B   USB_MODE_CTL;                                      		// 0x09
   	AIT_REG_B   USB_BIST_EN;                                          	// 0x0A
   	AIT_REG_B   USB_BIST_STS;                                          	// 0x0B
   	AIT_REG_B                   _0x0C[0x4];								//0x0C~0x0F reserved
   	
   	AIT_REG_B   USB_PHY_SPI_CTL0;                                       // 0x10
   	AIT_REG_B                   _0x11[0x1];								// 0x11
   	AIT_REG_B   USB_PHY_SPI_CTL1;                                       // 0x12
   	AIT_REG_B   USB_PHY_SPI_CTL2;                                       // 0x13
   	AIT_REG_B                   _0x14[0x28];							//0x14~0x3B reserved
   	AIT_REG_B   USB_OTG_TM;                                          	// 0x3C
   	AIT_REG_B   USB_OTG_CTL;                                          	// 0x3D
   	AIT_REG_B   USB_OTG_SRAM_CTL;                                       // 0x3E
   	AIT_REG_B                   _0x3F[0x1];								// 0x3F
   	
   	
   	AIT_REG_B   USB_UTMI_CTL0;                                         	// 0x40
   	AIT_REG_B   USB_UTMI_CTL1;                                          // 0x41
   	AIT_REG_B   USB_UTMI_CTL2;                                          // 0x42
   	AIT_REG_B   USB_UTMI_CTL3;                                          // 0x43
   	AIT_REG_B   USB_UTMI_CTL4;                                         	// 0x44
   	AIT_REG_B                   _0x45[0xB];
   	
   	
   	AIT_REG_B   USB_FARADAY_PHY_CTL0;                                   // 0x50
   	AIT_REG_B   USB_FARADAY_PHY_CTL1;                                   // 0x51
   	AIT_REG_B   USB_FARADAY_PHY_CTL2;                                   // 0x52
   	AIT_REG_B                   _0x53[0x11];							// 0x53~0x63 reserved
   	AIT_REG_D	USB_SOF_CNT;
   	AIT_REG_B                   _0x68[0x18];							// 0x68~0x7F reserved
   	AIT_REG_B	USB_DMA_CTL;											// 0x80
   	AIT_REG_B	USB_DMA_DESC_CNT;										// 0x81
   	AIT_REG_B	USB_DMA_INT_EN;											// 0x82
   	AIT_REG_B	USB_DMA_INT_STS;										// 0x83
   	AIT_REG_D	USB_DMA_FB_ST_ADDR;										// 0x84
   	AIT_REG_B	USB_DMA_FIXED_DATA;										// 0x88
   	AIT_REG_B					_0x89[0x1];								// 0x89 reserved
   	AIT_REG_W	USB_DMA_CMD_ADDR;										// 0x8A
   	AIT_REG_B                   _0x8C[0x8];								// 0x8C~0x93 reserved
   	AIT_REG_D	USB_DMA_TAR_AND_VAL;									// 0x94
   	AIT_REG_D	USB_DMA_TAR_OR_VAL;										// 0x98
   	AIT_REG_B                   _0x9C[0x14];							// 0x9C~0xAF reserved
   	AIT_REG_B	USB_CLK_GATED_SEL;										// 0xB0
   	AIT_REG_B                   _0xB1[0x0F];							// 0xB1~0xBF reserved
   	AIT_REG_B	USB_INCOMPTX_CTL;										// 0xC0
   	AIT_REG_B					_0xC1[0x1];								// 0xC1 reserved
   	AIT_REG_B	USB_EP_DISABLE;											// 0xC2
   	AIT_REG_B                   _0xC3[0xD];								// 0xC3~0xCF reserved
   	AIT_REG_B	USB_DMA_INT2_EN;
   	AIT_REG_B	USB_DMA_INT2_STS;
   	AIT_REG_B					_0xD2[0x2];								// 0xD2~0xD3 reserved
   	AIT_REG_W	USB_PKT_BYTE_CNT;
} AITS_USB_DMA, *AITPS_USB_DMA;

union USB_FIFO_RW{
	AIT_REG_B FIFO_B;
	AIT_REG_W FIFO_W;
	AIT_REG_D FIFO_D;
};

typedef struct _AITS_USB_EP {
   	AIT_REG_W   USB_EP_TX_MAXP;
   	AIT_REG_W   USB_EP_TX_CSR; 
  	AIT_REG_W   USB_EP_RX_MAXP; 
   	AIT_REG_W   USB_EP_RX_CSR; 
   	AIT_REG_W   USB_EP_COUNT;
   	AIT_REG_B                   _0x9[0x5]; 
   	AIT_REG_B   USB_CFG_DATA; 
} USB_EP_CTL, *USBS_EP_CTL;

// *****************************************************************************
//   USB DMA register structure (0x8000 A800)
// *****************************************************************************
typedef struct _AITS_USB_CTL {
   	AIT_REG_B   USB_FADDR;                                          		// 0x00
   	AIT_REG_B   USB_POWER;                                          		// 0x01
   	AIT_REG_W   USB_TX_INT_STS;                                          	// 0x02
   	AIT_REG_W   USB_RX_INT_STS;                                          	// 0x04
   	AIT_REG_W   USB_TX_INT_EN;                                          	// 0x06
   	AIT_REG_W   USB_RX_INT_EN;                                          	// 0x08
   	AIT_REG_B   USB_INT_EVENT_STS;                                          // 0x0A
   	AIT_REG_B   USB_INT_EVENT_EN;                                          	// 0x0B
   	AIT_REG_W   USB_FRAME_NUM;                                          	// 0x0C
   	AIT_REG_B   USB_INDEX_EP_SEL;                                          	// 0x0E
   	AIT_REG_B   USB_TESTMODE;                                          		// 0x0F
   	USB_EP_CTL	USB_INDEX_EP[0x1];  	   									// 0x10
   	union USB_FIFO_RW   USB_FIFO_EP[0x6];                                   // 0x20
   	AIT_REG_B                   _0x38[0x34]; 								// 0x30~0x6B
   	AIT_REG_W   USB_ADT_HW_VER;                                     		// 0x6C
   	AIT_REG_B                   _0x6E[0xA]; 
   	AIT_REG_B   USB_ADT_EP_INFO;                                          	// 0x78
   	AIT_REG_B   USB_ADT_RAM_INFO;                                          	// 0x79
   	AIT_REG_B   USB_ADT_LINK_INFO;                                          // 0x7A
   	AIT_REG_B   USB_ADT_VP_LEN;                                          	// 0x7B
   	AIT_REG_B   USB_ADT_HS_EOF;                                          	// 0x7C
   	AIT_REG_B   USB_ADT_FS_EOF;                                          	// 0x7D
   	AIT_REG_B   USB_ADT_LS_EOF;                                          	// 0x7E
   	AIT_REG_B   USB_ADT_SOFT_RST;                                          	// 0x7F
   	AIT_REG_B                   _0x80[0x80];
   	USB_EP_CTL	USB_EP[6];													// 0x100
   	AIT_REG_B                   _0x140[0x1E0]; 
   	AIT_REG_W   USB_RX_DPKBUFDIS;                                          	// 0x340
   	AIT_REG_W   USB_TX_DPKBUFDIS;                                          	// 0x342
   	AIT_REG_W   USB_UCH;                                          			// 0x344
   	AIT_REG_W   USB_HSRTN;                                          		// 0x346
  
} AITS_USB_CTL, *AITPS_USB_CTL;
#endif

////////////////////////////////////
// Register definition
//

#if !defined(BUILD_FW)
// DMA OPR

#if (CHIP == P_V2)||(CHIP == VSN_V2)

#endif

#endif
/// @}

#endif // _MMPH_REG_USB_H_
